Lehrstuhl für Technische Informatik


Keynote: Prof. Dr. Zebo Peng

Embedded Systems Lab

University of Linköping, Sweden

Web: http://www.ida.liu.se/~zebpe/

Hardening or Not Hardening: Is This the Question?


More and more embedded systems are used nowadays for safety-critical applications with stringent reliability requirements. At the same time, with silicon technology scaling, integrated circuits are implemented with smaller transistors, operate at higher clock frequency, and run at lower voltage levels. As a result, they are subject to more faults and interferences. We are therefore facing the challenge of how to build reliable embedded systems with unreliable components. One approach to address this challenge is to use hardware hardening techniques to make them more fault tolerant.

Traditionally, research on fault tolerance has mainly dealt with permanent faults. However, in nano-scale technology, we have more often transient faults, caused mainly by cosmic radiation, alpha-particles, electromagnetic interference, static electrical discharges, power supply fluctuations, temperature variation, etc. Recent studies have indicated that the rate of transient faults is increasing rapidly in modern electronic systems. While several hardware architectural solutions (including hardware hardening), proposed to tolerate permanent faults, may be used for tolerating transient faults, they are only efficient if the number of transient faults is not very large. An alternative is therefore to use software-based techniques such as re-execution. However, these techniques often introduce significant time overhead which can cause tasks in a real-time application to miss their deadlines.

This presentation will discuss the design of embedded systems for safety-critical applications by considering both fault-tolerance and real-time requirements at the same time. It will present several key challenges and some solutions to the design and optimization of such systems. In particular, it will present the trade-off between hardening in hardware and process re-execution in software. It will answer the questions of if hardening should be done and how much hardening should be implemented. The presentation will also address several challenges associated with the testing of such systems and some emerging solutions.

Speaker's Biography:

Zebo Peng received his Ph.D. degree in Computer Science from Linköping University in 1987. He has been Professor of Computer Systems and Director of the Embedded Systems Laboratory at Linköping University since 1996. He was Director of the Swedish National Graduate School in Computer Science in 2006-2008.

Prof. Peng's research interests include design and test of embedded systems, electronic design automation, SoC testing, fault tolerant design, hardware/software co-design, and real-time systems. He has published over 250 technical papers and four books in these areas. He received four best paper awards, two at the European Design Automation Conferences (1992, 1994), one at the IEEE Asian Test Symposium (2002), and one at the Design, Automation and Test in Europe Conference (2005), as well as a best presentation award at the International Conference on Hardware/Software Codesign and System Synthesis (2003). Two of his publications have been selected as the most influential papers of 10 years of DATE (the Design, Automation, and Test in Europe Conference).

Prof. Peng serves currently as Associate Editor of the IEEE Transactions on VLSI Systems, the VLSI Design Journal, and the EURASIP Journal on Embedded Systems. He has served on the program committee of a dozen international conferences and symposiums, including ATS, DATE, DDECS, DFT, ETS, IOLTS, RTCSA, and VLSI-SOC, and was the Program Chair of ETS’07 and DATE'08. He served as the Chair of the IEEE European Test Technology Technical Council (ETTTC) in 2006-2009, and has been a Golden Core Member of the IEEE Computer Society since 2005.

Invited Talk: Dr. Pete Harrod

ARM Ltd., Cambridge, UK

Test, Reliability and Safety Aspects of Embedded Processors


Embedded processors are used in many applications that demand a high level of reliability and availability. This presentation will cover some of the features that are designed in to embedded CPUs in order to satisfy the challenging requirements of, for example, the automotive, network and data storage markets. These include sophisticated error correction schemes to protect memory and interconnect against soft and hard errors and higher-level techniques such as running duplicate cores in lock-step.

Speaker's Biography:

Peter Harrod is a member of the CPU design team at ARM Ltd in Cambridge, where he was worked for the past 20 years. He has been involved in many aspects of processor design and has a special interest in the areas of test and reliability.